1. Field of the Invention
The present invention relates to semiconductor devices, and more specifically, to a semiconductor device having a connecting hole not larger than 0.4 .mu.m.quadrature. in size and an overlay mark. The present invention also relates to a method of manufacturing such a semiconductor device.
2. Description of the Background Art
In the manufacture of a semiconductor device, the higher integration and accompanying scaling down of the semiconductor device are making the width of a pattern line as well as the space between pattern lines smaller. In addition, strict overlay-accuracy for high density integration is required due to complication of the longitudinal structure of a device.
FIG. 11 is an illustration showing a conventional overlay technique. Overlapping is accomplished when a pattern on a photomask 20 is transferred to a wafer 21. More specifically, in the overlaying, the position of a wafer overlay mark 23 in diffraction grating form formed on the wafer is measured using alignment light 24 through photomask 20. The displacement between the position thus measured and a stage is corrected by moving the stage, and a chip pattern 25 on photomask 20 is transferred onto wafer 21 as a chip pattern 26a. It is noted that the wafer alignment pattern to be used for overlapping the next layer is also transferred at the same time.
There are at least two types of such overlay marks 22, one for the alignment in the X direction and the other in the Y direction.
For the high density integration and accompanying scaling down of a semiconductor device, a technique for forming a fine pattern using a halftone phase shift mask (hereinafter referred to as a halftone mask) as photomask 20 has been proposed.
With reference to FIG. 12, photomasks in general includes a usual mask and a phase shift mask. A halftone mask is known as an example of the phase shift mask. The usual mask is a glass plate on which a pattern formed of metal such as Cr or MoSi is formed. The halftone mask is a glass plate on which a metal pattern of MoSiON, CrON or the like is formed.
The halftone mask is provided with a material which inverts the phase of light passing through non-shading portions in the location corresponding to shading portions formed on the usual mask. The halftone mask enhances the light contrast of the pattern and forms a fine pattern as compared with the usual mask.
FIGS. 13A and 13B show the differences between the usual mask and the halftone mask. As for the halftone mask, the phase of light is inverted in the non-shading portion. The use of the halftone mask allows a pattern 26 and a peak 27 of light intensity to be clearly distinguished, thereby increasing resolution. A peak 28 of light intensity is however formed that can cause a ghost pattern as will be later described.
The problem associated with the manufacture of a semiconductor device by means of lithography technique using a conventional halftone mask will now be described.
With reference to FIG. 14, a connecting hole portion 29 and an overlay mark portion 30 are formed on a semiconductor substrate 9. A first oxide film 10, a barrier metal 11, an aluminum film 12, a titanium nitride film 13 and a second oxide film 14 are formed on semiconductor substrate 9 in connecting hole portion 29. First and second oxide films 10 and 14 are formed on semiconductor substrate 9 in overlay mark portion 30. Resist 15 for forming a connecting hole is provided in connecting hole portion 29. Resist 15b for forming an overlay mark is provided in overlay mark portion 30. A halftone mask 31 having non-shading portions in the positions to have a connecting hole and an overlay mark, respectively, is prepared. Halftone mask 31 has shading and non-shading portions 32 and 33 in overlay mark portion 30. Resist 15 is irradiated with light 34 using halftone mask 31. At this time, portions 35 and 36 to have a connecting hole and an overlay mark, respectively, are also exposed to the light. Further, a ghost pattern 37 is produced in the non-shading portion at the time. Ghost pattern 37 is formed by the phase-inverted light (corresponding to peak 28 in the light intensity) reflected by the surface of substrate 9 and directed upon resist 15b.
The formation of ghost pattern 37 will now be described in further detail. FIG. 22 shows changes in the reflectivity of the surface of an oxide film relative to changes in thickness when the oxide film is provided on a highly reflective substrate such as a silicon substrate. As is apparent from FIG. 22, the amplitude of the reflectivity caused by the change in the thickness of the oxide film is large. The change in the diameter of the opening portion of resist is accordingly large as shown in FIG. 23. The amplitude period of reflectivity corresponds to about 1240 .ANG. for a wavelength of 365 nm, and therefore the maximum and minimum values of reflectivity are within the range of the amplitude if the thickness of the oxide film changes by 620 .ANG.. Thus, the diameter of the opening portion of the resist largely changes. When an oxide film having a thickness around 10000 .ANG. is provided, the resist is inevitably exposed to light reflected from the silicon substrate due to the above mentioned change in the diameter if the thickness of the oxide film has a variation of 10% in its surface.
FIG. 24 is a graph showing the optimum exposure amount relative to the size of a connecting hole to be formed on the highly reflective substrate. The exposure amount allowing formation of a ghost pattern is also shown in FIG. 24. Herein, the abscissa represents the size of the connecting hole, and the optimum exposure amount given in FIG. 24 also applies to an overlay mark having a diameter of at least 1 .mu.m, which can be regarded as the same in terms of size to the connecting hole having a diameter of 1 .mu.m.
Assuming that the optimum exposure amount in the case of a connecting hole of 1 .mu.m.quadrature. is normalized as 1, 1.5 times of the optimum exposure amount is required for a connecting hole of 0.4 .mu.m.quadrature.. Then, the optimum exposure amount allowing formation of a ghost pattern is sufficiently between the normalized 1.5 and 1. With reference to FIG. 14, ghost pattern 37 is consequently formed in the overlay mark portion in forming connecting hole 35.
It is noted that the overlay mark can be well or poorly formed because of the variation in reflectivity as is apparent from FIGS. 22 and 23. This variation is the problem.
Returning to FIGS. 14, 15 and 16, development of resist 15 to form resist patterns 15a and 15b actually results in resist patterns 15a and 15b having an undesired void portion 38 caused by the light for forming a ghost pattern peculiar to a halftone mask as shown in FIG. 16 rather than those free from a void in a resist as shown in FIG. 15.
It is noted that the overlay mark is in a striped pattern having a width of 1 .mu.m and the size of the connecting hole is 0.4 .mu.m.quadrature..
With reference to FIGS. 16 and 17, etching oxide film 14 using resist patterns 15a and 15b as masks forms oxide films 16a and 16b having a connecting hole 39 and a pattern 40 of an oxide film to be an overlay mark, respectively. A poorly shaped resist pattern causes a void 141 to be formed in pattern 40 of the oxide film, that is, in the overlay mark.
With reference to FIG. 18, a second interconnection layer 41 is formed to contact with a titanium nitride film 13 though connecting hole 39. At the time, the component of the second interconnection layer is formed also in overlay mark portion 30. Resist 42 is applied to cover second interconnection 41.
Then, resist 42 is selectively exposed to light through a halftone mask using an overlay mark 40 as a reference for alignment to form a resist pattern 43. Although resist pattern 43 is a portion for patterning second interconnection layer 41, it is formed offset due to the poorly shaped overlay mark 40 as shown in FIG. 18.
With reference to FIGS. 18 and 19, resist 42 is developed to form resist pattern 43.
With reference to FIGS. 19 and 20, patterning of second interconnection layer 41 using resist pattern 43 as a mask forms second interconnection layer 41 disconnected from aluminum film 12, the first interconnection layer. It is noted that FIG. 21 is a cross section of a semiconductor device where the steps have ideally proceeded without having the above mentioned offset. In this case, second interconnection layer 41 is tightly connected to aluminum film 12 having titanium nitride film 13 interposed.
The above mentioned disconnection causes yield to decrease in the manufacture of a semiconductor device.